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general description the max1513/max1514 provide complete power-sup- ply solutions for active-matrix thin-film transistor (tft) liquid-crystal displays (lcds). both devices include a high-performance step-up regulator controller, three lin- ear-regulator controllers, and an adjustable delay block for startup sequencing. the max1513 includes an additional linear-regulator controller and a high-perfor- mance buffer amplifier. the max1513/max1514 can operate from 2.7v to 5.5v input supplies and provide overload protection with timer delay latch on all the reg- ulated outputs. the step-up regulator controller drives an external n- channel mosfet to generate the regulated supply volt- age for the panel source-driver ics. its current-mode control architecture provides fast transient response to pulsed loads. the high switching frequency (up to 1.5mhz) allows the use of ultra-small inductors and ceramic capacitors while achieving efficiencies over 85% using lossless current sensing. the internal soft-start lim- its the input surge current during startup. the gate-on and gate-off linear-regulator controllers of the max1513/max1514 provide regulated tft gate-on and gate-off supplies. the gate-on supply is activated after an adjustable delay following the step-up regulator. the logic linear-regulator controller can be used to cre- ate a low-voltage logic supply. the gamma linear-regula- tor controller of the max1513 can be used to generate a gamma-correction reference supply or another general- purpose supply rail. the max1513? high-performance buffer amplifier can drive the lcd backplane (vcom) or the gamma-correction divider string. the max1513/max1514 are available in 4mm ? 4mm 20-pin thin qfn packages with a maximum thickness of 0.8mm, suitable for ultra-thin lcd panel design. applications notebook computer displays lcd monitors and tvs automotive displays features ? 2.7v to 5.5v input supply range ? input-supply undervoltage lockout ? current-mode step-up controller fast transient response to pulsed load high efficiency lossless current sensing 430khz/750khz/1.5mhz switching frequency ? linear-regulator controllers for v gon , v goff ? linear-regulator controller for logic supply ? high-performance buffer amplifier (max1513 only) ? additional linear-regulator controller (max1513 only) ? power-up sequence and v gon delay control ? v main , v gon , v goff , v gamma shutdown control ? timer-delay fault latch for all outputs ? thermal-overload protection max1513/max1514 tft-lcd power-supply controllers ________________________________________________________________ maxim integrated products 1 ordering information 19-3047; rev 0; 10/03 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. part temp range pin-package max1513 etp -40 c to +85 c 20 thin qfn 4mm x 4mm max1514 etp -40 c to +85 c 20 thin qfn 4mm x 4mm pin configuration appears at end of data sheet. evaluation kit available max1513 max1514 sdfr in v gamma v in del drvl fbl v logic v main drvg fbg supb fbpb outb to vcom v main v goff v gon cs+ cs- gate gnd fb drvp fbp drvn fbn ref minimal operating circuit
max1513/max1514 tft-lcd power-supply controllers 2 _______________________________________________________________________________________ absolute maximum ratings stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. fb, fbp, fbn, fbg, fbl, in, cs+, cs-, sdfr to gnd ...............................................-0.3v to +6v del, gate, ref to gnd .............................-0.3v to (v in + 0.3v) supb to gnd .........................................................-0.3v to +14v outb, fbpb to gnd ..............................-0.3v to (v supb + 0.3v) drvp, drvg, drvl to gnd ..................................-0.3v to +30v drvn to gnd .....................................(v in - 28v) to (v in + 0.3v) outb continuous output current .................................... 75ma continuous power dissipation (t a = +70 c) 20-pin tqfn (derate 16.9mw/? above +70?) .......1349mw operating temperature range ...........................-40? to +85? junction temperature ......................................................+150? storage temperature range .............................-65? to +150? lead temperature (soldering, 10s) .................................+300? electrical characteristics (circuit of figure 1, v in = 3v, v supb = 10v, sdfr = in, c ref = 0.22?, t a = 0? to +85? . typical values are at t a = +25?, unless otherwise noted.) parameter symbol conditions min typ max units in supply range v in 2.7 5.5 v v in rising 2.5 2.7 2.9 in undervoltage-lockout threshold v uvlo 350mv typical hysteresis v in falling 2.2 2.35 2.5 v in quiescent current i in v fb = v fbp = v fbl = v fbg = 1.5v, v fbn = 0 1.25 ma in shutdown current v sdfr = 0, v fbl = 1.5v 150 ? ref output voltage -2? < i ref < 100?, 2.7v < v in < 5.5v 1.231 1.250 1.269 v temperature rising +160 thermal shutdown hysteresis 15 c duration to trigger fault latch 43.6 ms main step-up controller sdfr = in 1.275 1.500 1.725 sdfr = ref 0.60 0.75 0.90 operating frequency f osc sdfr = unconnected 0.43 mhz oscillator maximum duty cycle 80 85 90 % fb regulation voltage v fb v cs+ - v cs- = 0 1.237 1.25 1.263 v fb fault trip level v fb falling 0.96 1.00 1.04 v fb load regulation 0 < (v cs+ - v cs- ) < 50mv -1 % fb line regulation v in = 2.7v to 5.5v 0.1 0.2 % / v fb input bias current v fb = 1.5v -100 +100 na cs+ input current 2.2v < v cs+ < 6v 90 ? cs- input current 2.2v < v cs- < 6v -1 +1 ? current-limit threshold v cs+ - v cs- , 2.2v < v cs+ < 6v 100 125 150 mv gate-drive output high or low 3 5 ? soft-start period t ss 2.7 ms soft-start step size v ref / 128 v gate-on linear-regulator controller (reg p) fbp regulation voltage v fbp i drvp = 50? 1.225 1.250 1.275 v fbp fault trip level v fbp falling 0.96 1.00 1.04 v fbp input bias current v fbp = 1.5v -250 +250 na
max1513/max1514 tft-lcd power-supply controllers _______________________________________________________________________________________ 3 electrical characteristics (continued) (circuit of figure 1, v in = 3v, v supb = 10v, sdfr = in, c ref = 0.22?, t a = 0? to +85? . typical values are at t a = +25?, unless otherwise noted.) parameter symbol conditions min typ max units fbp effective load-regulation error (transconductance) v drvp = 10v, i drvp = 25? to 500? -1.5 -2 % fbp line (in)-regulation error i drvp = 50?, 2.7v < v in < 5.5v 8 mv drvp sink current i drvp v fbp = 1.1v, v drvp = 10v 1 ma drvp off-leakage current v fbp = 1.5v, v drvp = 28v 0.15 10 ? del charge current during startup, v del = 1.0v 4 5 6 a del turn-on threshold v th ( del ) 1.19 1.25 1.31 v del discharge switch on-resistance v in = 3.0v, v fb = 0.8v 15 ? soft-start period t ss 2.7 ms soft-start step size v ref / 128 v gamma linear-regulator controller (reg g, max1513 only) fbg regulation voltage v fbg i drvg = 0.35ma 1.235 1.250 1.265 v fbg to fb regulation voltage matching i drvg = 0.5ma, v cs+ - v cs- = 0 -1.2 +1.2 % fbg fault trip level v fbg falling 0.96 1.00 1.04 v fbg input bias current v fbg = 1.5v -250 +250 na fbg effective load-regulation error (transconductance) v drvg = 10v, i drvg = 0.175ma to 3.5ma -1.5 -2 % fbg line (in)-regulation error i drvg = 0.5ma, 2.7v < v in < 5.5v 5 mv drvg sink current i drvg v fbg = 1.1v, v drvg = 10v 5 ma drvg off-leakage current v fbg = 1.5v, v drvg = 28v 0.15 10 ? soft-start period t ss 2.7 ms soft-start step size v ref / 128 v logic linear-regulator controller (reg l) fbl regulation voltage v fbl i drvl = 0.8ma 1.225 1.250 1.275 v fbl fault trip level v fbl falling 0.96 1.00 1.04 v fbl input bias current v fbl = 1.5v -250 +250 na fbl effective load-regulation error (transconductance) v drvl = 3v, i drvl = 0.4ma to 8ma -1.5 -2 % fbl line (in)-regulation error i drvl = 1ma, 2.7v < v in < 5.5v 8 mv drvl sink current i fbl v fbl = 1.1v, v drvl = v in 15 20 ma drvl off-leakage current v fbl = 1.5v, v drvl = 28v 0.15 10 ? soft-start period t ss 2.7 ms soft-start step size v ref / 128 v
max1513/max1514 tft-lcd power-supply controllers 4 _______________________________________________________________________________________ electrical characteristics (continued) (circuit of figure 1, v in = 3v, v supb = 10v, sdfr = in, c ref = 0.22?, t a = 0? to +85? . typical values are at t a = +25?, unless otherwise noted.) parameter symbol conditions min typ max units gate-off linear-regulator controller (reg n) fbn regulation voltage v fbn i drvn = 0.2ma 220 250 280 mv fbn fault trip level v fbn rising 380 420 460 mv fbn input bias current v fbn = 0v -250 +250 na fbn effective load-regulation error (transconductance) v drvn = -10v, i drvn = 0.1ma to 2ma 18 25 mv fbn line (in)-regulation error i drvn = 0.2ma, 2.7v < v in < 5.5v 5 mv drvn source current i fbn v fbn = 0.3v, v drvn = -10v 5 ma drvn off-leakage current v fbn = -0.1v, v drvn = -20v 0.1 10 ? soft-start period t ss 2.7 ms soft-start step size v ref / 128 v buffer amplifier supb supply range v supb 4.5 13.0 v supb supply current i supb no load, v fbpb = 4v 0.75 1.1 ma fbpb input offset voltage v os v fbpb = v supb / 2 0 12 mv fbpb input bias current i bias v fbpb = v supb / 2 50 na fbpb input common-mode range v cm 0 v supb v common-mode rejection ratio cmrr 0 < v fbpb < v supb 50 db output-voltage-swing high v oh i outb = 5ma v supb - 150 v supb - 80 mv output-voltage-swing low v ol i outb = -5ma 80 150 mv short-circuit current 50 150 ma power-supply rejection ratio psrr dc, 6v v supb 13v, v fbpb = 4v 60 80 db slew rate 10 v/? -3db bandwidth r l = 10k ? , c l = 10pf 12 mhz control inputs and outputs sdfr = in (1.5mhz operation) 0.9 v in sdfr = unconnected (430khz operation) 0.69 v in 0.77 v in sdfr = ref (750khz operation) 1.00 1.35 sdfr input level sdfr = gnd (lcd shutdown) 0.5 v sdfr = in +3.0 sdfr = ref -3.0 sdfr input current sdfr = gnd -3.0 ?
max1513/max1514 tft-lcd power-supply controllers _______________________________________________________________________________________ 5 electrical characteristics (circuit of figure 1, v in = 3v, v supb = 10v, sdfr = in, c ref = 0.22?, t a = -40? to +85? , unless otherwise noted.) (note 1) parameter symbol conditions min typ max units in supply range v in 2.7 5.5 v v in rising 2.5 2.9 in undervoltage-lockout threshold v uvlo 350mv typical hysteresis v in falling 2.2 2.5 v in quiescent current i in v fb = v fbp = v fbl = v fbg = 1.5v, v fbn = 0 1.25 ma ref output voltage -2? < i ref < 100?, 2.7v < v in < 5.5v 1.225 1.275 v main step-up controller sdfr = in 1.275 1.725 operating frequency f osc sdfr = ref 0.60 0.90 mhz fb regulation voltage v fb v cs+ - v cs- = 0 1.230 1.270 v fb line regulation v in = 2.7v to 5.5v 0.2 % / v fb input bias current v fb = 1.5v -100 +100 na cs+ input current 2.2v < v cs+ < 6v 90 ? cs- input current 2.2v < v cs- < 6v -1 +1 ? current-limit threshold v cs+ - v cs- , 2.2v < v cs+ < 6v 100 150 mv gate-drive output high or low 5 ? gate-on linear-regulator controller (reg p) fbp regulation voltage v fbp i drvp = 0.1ma 1.225 1.275 v fbp input bias current v fbp = 1.5v -250 +250 na fbp effective load-regulation error (transconductance) v drvp = 10v, i drvp = 0.05ma to 1ma -2 % drvp sink current i drvp v fbp = 1.1v, v drvp = 10v 2 ma del turn-on threshold v th ( del ) 1.19 1.31 v gamma linear-regulator controller (reg g, max1513 only) fbg regulation voltage v fbg i drvg = 0.5ma 1.235 1.265 v fbg to fb regulation voltage matching i drvg = 0.5ma, v cs+ - v cs- = 0 -1.2 +1.2 % fbg input bias current v fbg = 1.5v -250 +250 na fbg effective load-regulation error (transconductance) v drvg = 10v, i drvg = 0.25ma to 5ma -2 % drvg sink current i drvg v fbg = 1.1v, v drvg = 10v 10 ma
max1513/max1514 tft-lcd power-supply controllers 6 _______________________________________________________________________________________ electrical characteristics (continued) (circuit of figure 1, v in = 3v, v supb = 10v, sdfr = in, c ref = 0.22?, t a = -40? to +85? , unless otherwise noted.) (note 1) parameter symbol conditions min typ max units logic linear-regulator controller (reg l) fbl regulation voltage v fbl i drvl = 1ma 1.225 1.275 v fbl input bias current v fbl = 1.5v -250 +250 na fbl effective load-regulation error (transconductance) v drvl = 3v, i drvl = 0.5ma to 10ma -2 % drvl sink current i fbl v fbl = 1.1v, v drvl = v in 20 ma gate-off linear-regulator controller (reg n) fbn regulation voltage v fbn i drvn = 0.2ma 220 280 mv fbn input bias current v fbn = 0v -250 +250 na fbn effective load-regulation error (transconductance) v drvn = -10v, i drvn = 0.1ma to 2ma 25 mv drvn source current i fbn v fbn = 0.3v, v drvn = -10v 5 ma buffer amplifier supb supply range v supb 4.5 13.0 v supb supply current i supb no load, v fbpb = 4v 1.1 ma fbpb input offset voltage v os v fbpb = v supb / 2 12 mv fbpb input bias current i bias v fbpb = v supb / 2 50 na fbpb input common-mode range v cm 0 v supb v output-voltage-swing high v oh i outb = 5ma v supb - 150 mv output-voltage-swing low v ol i outb = -5ma 150 mv control inputs and outputs sdfr = in (1.5mhz operation) 0.9 v in sdfr = unconnected (430khz operation) 0.69 v in 0.77 v in sdfr = ref (750khz operation) 1.00 1.35 sdfr input level sdfr = gnd (lcd shutdown) 0.5 v sdfr = in +3.0 sdfr = ref -3.0 sdfr input current sdfr = gnd -3.0 ? note 1: specifications to -40? are guaranteed by design, not production tested.
max1513/max1514 tft-lcd power-supply controllers _______________________________________________________________________________________ 7 typical operating characteristics (circuit of figure 1, v in = 5v, v main = 15v, v gon = 25v, v goff = -10v, v logic = 3.3v, v gamma = 14.7v, t a = +25?, unless other- wise noted.) step-up output voltage vs. load current max1513/14 toc02 load current (ma) output voltage (v) 600 500 400 300 200 100 14.7 14.8 14.9 15.0 15.1 14.6 0700 v in = 5v v in = 15v f osc = 1.5mhz step-up efficiency vs. load current (1.5mhz) max1513/14 toc01 load current (ma) efficiency (%) 700 600 500 400 300 200 100 50 60 70 80 90 100 40 0800 v in = 5.0v v in = 2.7v v in = 3.3v step-up regulator load-transient response max1513/14 toc03 4 s/div v main 100mv ac-coupled i main 500ma/div 0.1a i l 1a/div 0a step-up regulator pulsed-load-transient response max1513/14 toc04 4 s/div v main 100mv/div ac-coupled i main 1a/div 0.1a i l 1a/div 0a step-up regulator soft-start max1513/14 toc05 400 s/div v main 5v/div 0v i l 2a/div 0a power-up sequence max1513/14 toc06 4ms/div v logic 5v/div v main 20v/div v gon 20v/div v goff 10v/div v gamma 20v/div 0v 0v 0v 0v 0v linear regulator reg l load-transient response max1513/14 toc07 20 s/div v logic 50mv/div ac-coupled i logic 500ma/div 0ma buffer-amplifier supply current vs. supply voltage max1513/14 toc08 supply voltage (v) supply current (ma) 12 10 8 6 0.2 0.4 0.6 0.8 1.0 1.2 0 414 no load v fbpb = v supb / 2 buffer-amplifier small-signal step response max1513/14 toc09 400ns/div v fbpb 50mv/div ac-coupled v outb 50mv/div ac-coupled
max1513/max1514 tft-lcd power-supply controllers 8 _______________________________________________________________________________________ pin description name pin max1513 max1514 function 1 ref ref internal reference. connect a 0.22? ceramic capacitor from ref to the analog ground plane, which is connected to gnd. external load capability is at least 100?. 2 sdfr sdfr lcd shutdown and frequency-select input. sdfr = gnd, lcd shutdown, ref, buffer amplifier and the logic regulator (reg l) output stay on sdfr = in, 1.5mhz switching frequency sdrf = ref, 750khz switching frequency sdfr = unconnected, 430khz switching frequency 3 fbpb n.c. buffer-amplifier noninverting input for the max1513. not internally connected for the max1514. 4 outb n.c. buffer-amplifier output for the max1513. not internally connected for the max1514. 5 supb n.c. buffer-amplifier supply input for the max1513. bypass to gnd with a 0.1? capacitor. not internally connected for the max1514. 6 fbn fbn gate-off linear regulator (reg n) feedback input. fbn regulates to 125mv nominal. connect to the center tap of a resistive voltage-divider between the reg n output and the reference voltage (ref) to set the output voltage. place the resistive-divider close to this pin. 7 del del delay-control timing capacitor. connect a capacitor from del to gnd to set the gate-on linear- regulator startup delay. see the power-up sequence and delay control block section. buffer-amplifier large-signal step response max1513/14 toc10 1 s/div v fbpb 5v/div ac-coupled v outb 5v/div ac-coupled buffer-amplifier load-transient response max1513/14 toc11 1 s/div v outb 1v/div ac-coupled i outb 50ma/div 0ma typical operating characteristics (continued) (circuit of figure 1, v in = 5v, v main = 15v, v gon = 25v, v goff = -10v, v logic = 3.3v, v gamma = 14.7v, t a = +25?, unless other- wise noted.)
max1513/max1514 tft-lcd power-supply controllers _______________________________________________________________________________________ 9 pin description (continued) name pin max1513 max1514 function 8 drvn drvn reg n base drive. open drain of an internal p-channel mosfet. connect to the base of an external npn linear-regulator pass transistor. 9 drvl drvl logic linear-regulator (reg l) base drive. open drain of an internal n-channel mosfet. connect to the base of an external pnp linear-regulator pass transistor. 10 fbl fbl reg l feedback input. fbl regulates to 1.25v (typ). connect to the center tap of a resistive voltage-divider between the reg l output and the analog ground plane to set the output voltage. place the resistive voltage-divider close to this pin. 11 drvg n.c. gamma linear-regulator (reg g) base drive for the max1513. open drain of an internal n-channel mosfet. connect to the base of an external pnp linear-regulator pass transistor. not internally connected for the max1514. 12 fbg n.c. reg g feedback input for max1513. fbg regulates to 1.25v (typ). connect to the center tap of a resistive voltage-divider between the reg g output and the analog ground plane to set the output voltage. place the divider close to the fbg pin. not internally connected for the max1514. 13 fbp fbp gate-on linear-regulator (reg p) feedback input. fbp regulates to 1.25v (typ). connect to the center tap of a resistive voltage-divider between the reg p output and the analog ground plane to set the output voltage. place the resistive-divider close to this pin. 14 drvp drvp reg p base drive. open drain of an internal n-channel mosfet. connect to the base of an external pnp linear-regulator pass transistor. 15 gnd gnd ground 16 gate gate external mosfet gate drive. drives the gate of the step-up switching regulator? mosfet. 17 in in supply input. in powers all the internal circuitry of the max1513/max1514. the input voltage range is from 2.7v to 5.5v. bypass with a 0.1? ceramic capacitor between in and gnd. place the capacitor within 5mm of in. 18 cs+ cs+ current-sense-comparator noninverting input. connect cs+ and cs- to the lossless current-sense network. see the lossless current sense section. 19 cs- cs- current-sense-comparator inverting input. connect cs+ and cs- to the lossless current-sense network. see the lossless current sense section. 20 fb fb main step-up regulator feedback input. fb regulates to 1.25v (typ). connect to the center tap of a resistive voltage-divider between the main output (v main ) and the analog ground plane to set the main step-up regulator output voltage. place the resistive-divider close to this pin.
max1513/max1514 tft-lcd power-supply controllers 10 ______________________________________________________________________________________ cs+ cs- gate in sdfr del drvl fbl 16 19 18 15 v in 4.5v to 5.5v l1 2.2 h d1 c1 22 f 6.3v r1 110k ? r2 10.0k ? r11 10 ? 10 f q1 680 ? r7 16.5k ? r8 10.0k ? v main 15v/400ma v logic 3.3v/500ma lx 9 10 470pf 909 ? open 1m ? drvp fbp q3 6.8k ? r5 191k ? r6 10.0k ? lx 14 13 d3 drvg fbg q4 1.5k ? r9 107k ? r10 10.0k ? 11 12 fb 20 gnd outb fbpb supb 5 3 4 7 n1 drvn fbn lx 0.47 f q2 3.6k ? r3 102k ? r4 10.0k ? d2 8 6 0.1 f 0.1 f ref 1 to vcom backplane v gamma 14.7v/30ma 0.1 f 17 2 0.47 f 0.22 f v goff -10v/30ma v gon 25v/20ma 0.1 f c10 1 f 2.2 f c2 10 f 16v 0.1 f 0.47 f 0.1 f 0.1 f 0.47 f max1513 figure 1. typical operating circuit of the max1513
max1513/max1514 tft-lcd power-supply controllers ______________________________________________________________________________________ 11 figure 2. typical operating circuit of the max1514 cs+ cs- gate in sdfr del drvl fbl 16 19 18 15 v in 4.5v to 5.5v l1 2.2 h d1 c1 22 f 6.3v r1 110k ? r2 10.0k ? r11 10 ? 10 f q1 680 ? r7 16.5k ? r8 10.0k ? v main 15v/400ma v logic 3.3v/500ma lx 9 10 909 ? open drvp fbp q3 6.8k ? r5 191k ? r6 10.0k ? lx 14 13 d3 fb 20 gnd 7 n1 drvn fbn lx 0.47 f q2 3.6k ? r3 102k ? r4 10.0k ? d2 8 6 0.1 f 0.1 f ref 1 0.1 f 17 2 0.47 f 0.22 f v goff -10v/30ma v gon 25v/20ma c10 1 f 2.2 f 0.1 f 0.1 f 0.47 f max1514 c2 10 f 16v 470pf 1m ?
max1513/max1514 tft-lcd power-supply controllers 12 ______________________________________________________________________________________ cs+ cs- gate gnd fb main step-up controller with soft-start and fault comparator reg p with soft-start and fault comparator reg n with soft-start and fault comparator reference thermal shutdown drvp fbp drvn fbn ref op-amp control block reg g with soft-start and fault comparator reg l with soft-start and fault comparator sdfr del drvl fbl drvg fbg supb fbpb outb to vcom v gamma v main v logic v in v in v main v gon v goff max1513 max1514 max1513 only figure 3. max1513/max1514 functional diagram
max1513/max1514 tft-lcd power-supply controllers ______________________________________________________________________________________ 13 typical operating circuit the typical operating circuit of the max1513 (figure 1) is a complete power-supply system for tft lcds. the cir- cuit generates a +15v source-driver supply, +25v and -10v gate-driver supplies, a +3.3v logic supply for the timing controller, a 14.7v gamma-correction string supply and a vcom buffer. the typical operating circuit of the max1514 (figure 2) is similar to that of the max1513 except the gamma-correction string supply and the vcom buffer have been eliminated. the input voltage range for the ic is from +2.7v to +5.5v. the typical oper- ating circuits?listed load currents are available from a +4.5v to +5.5v supply. table 1 lists recommended com- ponent options, and table 2 lists the component suppli- ers?contact information. detailed description the max1513 and max1514 contain a high-perfor- mance, step-up switching-regulator controller and three linear-regulator controllers (two positive and one nega- tive). the max1513 also includes an additional linear-reg- ulator controller and a high-current buffer amplifier. figure 3 shows the max1513/max1514 functional diagram. main step-up regulator controller the main step-up regulator controller drives an external n-channel power mosfet to generate the tft-lcd source-driver supply. the controller employs a current- mode, fixed-frequency pwm architecture to maximize loop bandwidth and provide fast transient response to pulsed loads found in source-driver applications. the multilevel control input sdfr sets the switching fre- quency to 430khz, 750khz, or 1.5mhz. the high switching frequency allows the use of low-profile induc- tors and ceramic capacitors to minimize the thickness of lcd panel designs, while maintaining high efficiency using a lossless current-sense method. the ic? built-in soft-start function reduces the inrush current during startup. the controller regulates the output voltage and the power delivered to the output by modulating the duty cycle (d) of the power mosfet in each switching cycle. the duty cycle of the mosfet is approximated by: figure 4 shows the functional diagram of the step-up regulator controller. the core of the controller is a multi- input summing comparator that sums three signals: the output-voltage error signal with respect to the reference voltage, the current-sense signal, and the slope-com- pensation ramp. on the rising edge of the internal clock, the controller sets a flip-flop, which turns on the external n-channel mosfet, applying the input voltage across the inductor. the current through the inductor ramps up linearly, storing energy in its magnetic field. once the sum of the feedback voltage error, slope compensation, and current-sense signals trip the mu lti- d vv v main in main - table 1. component list table 2. component suppliers d esig n a t io n description c1 22f 20% , 6.3v x 5r cer am i c cap aci tor ( 1206) tai yo y ud en jm k316bj226m l c2 10f 20% , 16v p os c ap ( d 10) s anyo 16aqu 10m d1 1a, 30v schottky diode (s-flat) toshiba crs02 d2, d3 200ma, 100v diodes (sot23) fairchild mmbt4148se l1 2.2?, 3.3a inductor sumida cls7d16np-2r2nc n1 3a, 20v n-channel mosfet (sot23) fairchild fdn339an q1 3a, 60v pnp bipolar transistor (sot23) fairchild nzt660 q2 200ma, 40v npn bipolar transistor (sot23) fairchild mmbt3904 q3, q4 200ma, 40v pnp bipolar transistors (sot23) fairchild mmbt3906 supplier phone fax website fairchild semiconductor 408-822-2000 408-822-2102 www.fairchildsemi.com sumida 847-545-6700 847-545-6720 www.sumida.com taiyo yuden 800-348-2496 847-925-0899 www.t-yuden.com tdk 847-803-6100 847-390-4405 www.component.tdk.com toshiba 949-455-2000 949-859-3963 www.toshiba.com
max1513/max1514 tft-lcd power-supply controllers 14 ______________________________________________________________________________________ input pwm comparator, the flip-flop is reset and the mosfet turns off. since the inductor current is continu- ous, a transverse potential develops across the inductor that turns on the diode (d1). the voltage across the inductor then becomes the difference between the out- put voltage and the input voltage. this discharge condi- tion forces the current through the inductor to ramp down, transferring the energy stored in the magnetic field to the output capacitor and the load. the n-channel mosfet is kept off for the rest of the clock cycle. current limiting and current-sense amplifier (cs+, cs-) the internal current-limit circuit resets the pwm flip-flop and turns off the external power mosfet whenever the voltage difference between cs+ and cs- exceeds 125mv (typ). the tolerance on this current limit is 20%. use the minimum value of the current limit to select components of the current-sense network. lossless current sense the lossless current-sense method uses the dc resis- tance (dcr) of the inductor as the sense element. figure 5 shows a simplified step-up regulator using the basic lossless current-sensing method. an rc network is connected in parallel with the step-up inductor (l). the voltage across the sense capacitor (c s ) is the input to the current-sense amplifier. to prevent the sense amplifier from seeing large common-mode switching voltages, the sense capacitor should always be connected to the nonswitching end of the inductor (i.e., the input of the step-up regulator). lossless current sense can be easily understood using complex frequency domain analysis. the voltage across the inductor is given by: where l is the inductance, r l is the dcr of the induc- tor, and i l is the inductor current. the voltage across the sense capacitor is given by: where r s is the series resistor in the sense network and c s is the sense capacitor. the above equation can be rewritten as: therefore, the sense capacitor voltage is directly pro- portional to the inductor current if the time constant of the rc sense network matches the time constant of the inductor/dcr. the sense method is equivalent to using a current-sense resistor that has the same value as the inductor dcr. v sl r sr c i sl r sr c ri if l r r c then the equation becomes vri s l ss l l ss ll l ss sll / , : = + + = + + = = 1 1 1 v sr c v s ss l = + 1 1 v i sl r ll l =+ () clock reset dominant ilim comparator s rq 125mv level shift slope_comp to fault logic 1.0v soft-start block ref fb cs- cs+ gate max1513 max1514 r l l inductor r s c s + v s - v in v main c s+ c s- gate gnd fb figure 4. step-up regulator-controller functional diagram figure 5. step-up regulator using lossless current sensing
max1513/max1514 tft-lcd power-supply controllers ______________________________________________________________________________________ 15 logic linear-regulator controller the logic linear-regulator controller (reg l) is an analog gain block with an open-drain n-channel output. it dri- ves an external pnp pass transistor with a 680 ? base- to-emitter resistor (figure 1). its guaranteed base-drive sink current is at least 10ma. the regulator, including transistor q1 in figure 1, uses a 10? ceramic output capacitor and is designed to deliver 500ma at 3.3v. other output voltages and currents are possible by scal- ing the pass transistor, input capacitor, and output capacitor. see the pass-transistor selection and stability requirements sections. reg l is typically used to generate low-voltage logic supplies for the timing controller and the digital sec- tions of the tft-lcd source/gate-drive ics. reg l is automatically enabled when the input voltage is above the uvlo threshold. each time it is enabled, the controller goes through a soft-start routine that ramps up its internal reference dac in 128 steps. gate-off linear-regulator controller the gate-off linear-regulator controller (reg n) is an ana- log gain block with an open-drain p-channel output. it dri- ves an external npn pass transistor with a 3.6k ? base-to-emitter resistor (figure 1). its guaranteed base- drive source current is at least 2ma. the regulator, including q2 in figure 1, uses a 0.47? ceramic output capacitor and is designed to deliver 30ma at -10v. other output voltages and currents are possible by scaling the pass transistor, input capacitor, and output capacitor. see the pass-transistor selection and stability require- ments sections. reg n is typically used to provide the tft-lcd gate dri- vers?gate-off voltage. a negative voltage can be pro- duced using a charge-pump circuit as shown in figure 1. reg n is enabled after the logic linear-regulator reg l soft-start has completed. each time it is enabled, the control goes through a soft-start routine that ramps down its internal reference dac from v ref to 250mv in about 100 steps. gate-on linear-regulator controller the gate-on linear-regulator controller (reg p) is an analog gain block with an open-drain n-channel output. it drives an external pnp pass transistor with a 6.8k ? base-to-emitter resistor (figure 1). its guaranteed base- drive sink current is at least 1ma. the regulator includ- ing q3 in figure 1 uses a 0.47? ceramic output capacitor and is designed to deliver 20ma at 25v. other output voltages and currents are possible by scaling the pass transistor, input capacitor, and output capacitor. see the pass-transistor selection and stability requirement s sections. reg p is typically used to provide the tft-lcd gate drivers?gate-on voltage. use a charge pump with as many stages as necessary to obtain a voltage exceed- ing the required gate-on voltage (see the selecting the number of charge-pump stages section). note that the voltage rating of the drvp output is 28v. if the charge- pump output voltage can exceed 28v, an external cas- code-connected npn transistor should be added (figure 6). alternately, the linear regulator can control an intermediate charge-pump state while regulating the final charge-pump output (figure 7). reg p is enabled after the step-up regulator soft-start has completed and the voltage on del exceeds 1.25v. each time it is enabled, the controller goes through a soft-start routine that ramps up its internal reference dac in 128 steps. max1513 max1514 drvp fbp v main from charge- pump output pnp pass transistor npn cascode transistor v gon figure 6. using an npn cascode for charge-pump output voltages > 28v max1513 max1514 drvp fbp 0.1 f 0.1 f 0.47 f 0.22 f lx v main 13v v gon 35v 6.8k ? 267k ? 1% 10.0k ? 1% q1 figure 7. linear regulator controls intermediate charge-pump stage
max1513/max1514 tft-lcd power-supply controllers 16 ______________________________________________________________________________________ gamma linear-regulator controller (max1513 only) the gamma linear-regulator controller reg g is an ana- log gain block with an open-drain n-channel output. it drives an external pnp pass transistor with a 1.5k ? base-to-emitter resistor (figure 1). its guaranteed base- drive sink current is at least 5ma. the regulator, includ- ing q4 in figure 1, uses a 0.47? ceramic output capacitor, and the controller is designed to deliver 40ma at 14.7v. other output voltages and currents are possible by scaling the pass transistor, input capacitor, and output capacitor. see the pass-transistor selection and stability requirement s sections. reg g is typically used to provide the tft-lcd gamma reference voltage, which is usually 0.3v below the source-drive supply voltage. reg g is enabled 2.7ms after reg p? soft-start has completed. each time it is enabled, the controller goes through a soft-start routine that ramps up its internal ref- erence dac in 128 steps. buffer amplifier (max1513 only) the max1513 includes a buffer amplifier that is typical- ly used to drive the lcd backplane (vcom) or the gamma-correction divider string. the buffer amplifier features 150ma output short-circuit current, 10v/? slew rate, and 12mhz bandwidth. the rail-to-rail input and output capability maximizes its flexibility. short-circuit current limit the max1513? buffer amplifier limits short-circuit cur- rent to approximately 150ma if the output is directly shorted to supb or to gnd. if the short-circuit condition persists, the junction temperature of the ic rises until it reaches the thermal-shutdown threshold (+160 c typ). once the junction temperature reaches the thermal- shutdown threshold, an internal thermal sensor immedi- ately sets the thermal fault latch, shutting off all the ic? outputs. the device remains inactive until the input volt- age is cycled below v uvlo . driving pure capacitive load the buffer amplifier is typically used to drive the lcd backplane (vcom) or the gamma-correction divider string. the lcd backplane consists of a distributed series capacitance and resistance, a load that can be easily driven by the buffer amplifier. when driving a pure capacitive load, the amplifier? gain peaking increases. a 5 ? to 50 ? resistor placed between outb and the capacitive load reduces peaking. undervoltage lockout the undervoltage-lockout (uvlo) circuit compares the voltage at the in pin with the uvlo threshold (2.7v ris- ing, 2.35v falling, typ) to ensure the input voltage is high enough for reliable operation. the 350mv (typ) hysteresis prevents supply transients from causing a restart. once the input voltage exceeds the uvlo ris- ing threshold, the ic is allowed to start. when the input voltage falls below the uvlo falling threshold, all the regulator outputs (including ref) are disabled until the input voltage exceeds the uvlo rising threshold. reference voltage (ref) the reference output is nominally 1.25v and can source at least 100? without degrading its accuracy (see the typical operating characteristics ). bypass ref with a 0.22? ceramic capacitor connected between ref and the analog ground plane (which connects to gnd). shutdown and oscillator- frequency selection the four-level logic input sdfr controls shutdown and oscillator-frequency selection. connecting sdfr to ground shuts off all the regulator outputs except the logic linear-regulator controller (reg l), buffer amplifier, and ref. connecting sdfr to in sets the oscillator frequen- cy to 1.5mhz. connecting sdfr to ref sets the oscilla- tor frequency to 750khz. leaving sdfr unconnected sets the oscillator frequency to 430khz. when sdfr is left unconnected, bypass the pin to ground with a 1000pf to 0.1? capacitor to prevent switching noise from coupling into the pin? high input impedance. note the soft-start period and the fault-timer period do not change with the oscillator frequency. power-up sequence and delay control block once the voltage on in exceeds the uvlo rising thresh- old (2.7v typ), the internal reference is enabled. with a 0.22? ref bypass capacitor, the reference reaches its regulation voltage of 1.25v in approximately 1ms. when the reference voltage is ready, the max1513/max1514 enable the logic linear regulator. the max1513 also enables the buffer amplifier at the same time. once the logic linear-regulator soft-start is completed, the max1513/max1514 enable the step-up regulator and reg n simultaneously. once the soft-start of the step-up regulator is completed, the max1513/max1514 enable the delay control block. an internal 5a current starts charging the timing capacitor on del. when the voltage on del reaches 1.25v, the max1513/max1514 enable reg p. with a 0.1f capacitor on del, the del voltage reaches 1.25v in about 25ms. the max1513 enables the gamma linear regulator 2.7ms after the soft-start of reg p is completed. rail-to-rail is a registered trademark of nippon motorola, ltd.
max1513/max1514 tft-lcd power-supply controllers ______________________________________________________________________________________ 17 soft-start each positive regulator (step-up regulator, reg p, reg l, and reg g) includes a 7-bit soft-start dac whose input is the reference, and whose output is stepped in 128 steps from zero up to the reference voltage. the soft-start dac of the negative regulator (reg n) steps from the reference down to 250mv in about 100 steps. the outputs of the soft-start dacs determine the set points of each regulator. the soft-start duration is 2.7ms (typ) for each positive regulator and about 2.2ms for the negative regulator. the soft-start is independent of the selected operating frequency. fault protection during steady-state operation, if the step-up regulator output or any of the linear-regulator outputs does not exceed its respective fault detection threshold, the max1513/max1514 activate an internal fault timer. if any condition or the combination of conditions indi- cates a continuous fault for the fault-timer duration (43.6ms typ), the max1513/max1514 set the fault latch, shutting down all the outputs except the refer- ence. once the fault condition is removed, toggle sdfr (below 0.4v) or cycle the input voltage (below 2.2v) to clear the fault latch and reactivate the device. the fault- detection circuit is disabled during the soft-start time of each regulator. thermal-overload protection the thermal-overload protection prevents excessive power dissipation from overheating the max1513/ max1514. when the junction temperature exceeds +160 c, a thermal sensor immediately activates the fault-protection circuit, which shuts down all the outputs except the reference, allowing the device to cool down. once the device cools down by approximately 15 c, cycle the input voltage (below the uvlo falling thresh- old) to clear the fault latch and reactivate the device. the thermal-overload protection protects the controller in the event of fault conditions. for continuous opera- tion, do not exceed the absolute maximum junction temperature rating of t j = +150 c. design procedure main step-up regulator inductor selection the minimum inductance value, peak current rating, and dc series resistance (dcr) are factors to consider when selecting the inductor. these factors influence the converter? efficiency, maximum output load capability, transient-response time, and output voltage ripple. size and cost are also important factors to consider. the maximum output current, input voltage, output volt- age, and switching frequency determine the inductor value. very high inductance values minimize the cur- rent ripple and therefore reduce the peak current, which decreases core losses in the inductor and i 2 r losses in the entire power path. however, large induc- tor values also require more energy storage and more turns of wire, which increases size and can increase i 2 r losses in the inductor. low inductance values decrease the size but increase the current ripple and peak current. finding the best inductor involves choos- ing the best compromise between circuit efficiency, inductor size, and cost. the equations used here include a constant, lir, which is the ratio of the inductor peak-to-peak ripple current to the average dc inductor current at the full load cur- rent. the best trade-off between inductor size and cir- cuit efficiency for step-up regulators generally has an lir between 0.3 and 0.5. however, depending on the ac characteristics of the inductor core material and the ratio of inductor resistance to other power-path resis- tances, the best lir can shift up or down. if the induc- tor resistance is relatively high, more ripple can be accepted to reduce the number of turns required and increase the wire diameter. if the inductor resistance is relatively low, increasing inductance to lower the peak current can decrease losses throughout the power path. if extremely thin high-resistance inductors are used, as is common for lcd panel applications, the best lir can increase to between 0.5 and 1.0. once an inductor is chosen, higher and lower values for the inductor should be evaluated for efficiency improvements in typical operating regions. determine the inductor value and peak current require- ment as follows: since the current delivered by charge pumps connect- ed to lx adds to the inductor current, calculate the effective maximum output current, i main(eff) : where i main(max) is the maximum output current including any gamma-regulator current, n neg is the number of negative charge-pump stages, n pos is the number of positive charge-pump stages, i neg is the negative charge-pump output current, and i pos is the positive charge-pump output current, assuming the pump source for i pos is v main . calculate the approximate inductor value using the typ- ical input voltage (v in ), the expected efficiency ( typ ) iini ni main eff main max neg neg pos pos () ( ) =+ ++ () 1
max1513/max1514 tft-lcd power-supply controllers 18 ______________________________________________________________________________________ taken from an appropriate curve in the typical operating characteristics , and an estimate of lir based on the above paragraphs: choose an available inductor value from an appropriate inductor family. calculate the maximum dc input cur- rent at the minimum input voltage (v in(min) ) using the following equation: the expected efficiency at that operating point ( min ) can be taken from an appropriate curve in the typical operating characteristics. calculate the ripple current at that operating point and the peak current required for the inductor: the inductor? saturation current rating and the max1513/max1514s?current limit (i lim ) should exceed i peak , and the inductor? dc current rating should exceed i in(dc, max) . considering the typical operating circuit, the maximum load current (i main(max) ) is 400ma for i main directly and 30ma for reg g to provide v gamma . the one- stage negative charge pump provides 30ma to reg n for v goff , and the one-stage positive charge pump provides 20ma to reg p for v gon . altogether, the effective maximum output current (i main(eff) ) is 500ma with a 15v output and a typical 5v input voltage. the switching frequency is set to 1.5mhz. choosing an lir of 0.6 and estimating efficiency of 85% at this operating point: using the circuit? minimum input voltage (4.5v) and estimating efficiency of 80% at that operating point: the ripple current and the peak current are: the inductor dcr should be low enough for reasonable efficiency. as a rule of thumb, do not allow the voltage drop across the inductor dcr to exceed a few percent of the input voltage at i peak . many notebook panel designs have height constraints on the components. if a thin inductor with the required current rating is not available, use two thin inductors in series or parallel. current-sense network selection after selecting the inductor, use the following steps to design the current-sense network for lossless current sensing. 1) calculate the rc time constant of the sense network using the typical inductance and typical dcr: 2) determine the component values of the sense net- work. select c s , and then calculate r s using: 3) calculate the worst-case high sense voltage over temperature using the maximum dcr value (r l(max) ) found in the inductor technical specifications: where i peak is the peak inductor current calculated in the inductor selection section, tc is the temperature coefficient of copper (0.5%/?) and ? t is the difference between the specified temperature for r l(max) and the maximum expected inductor temperature. 4) compare the calculated sense voltage with the mini- mum value of the current-limit threshold in the electrical characteristics (100mv). if the sense voltage is between 80mv and 100mv, use the current-sense configuration in figure 8 with the calculated c s and r s above. vir tct sense peak l max () = + () 1 ? r c s s = () = l r l typ i vvv h v mhz a ia a a ripple peak . . . . . . . . = () =+ 45 15 45 22 15 15 10 21 10 2 26 - i av v a in dc max (, ) . . . . = 05 15 45 08 21 l v v vv a mhz h . . . . . = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 5 15 15 5 05 15 085 06 22 2 - i vvv lv f ii i ripple in min main in min main osc peak in dc max ripple () () (, ) = () =+ - 2 i iv v in dc max main eff main in min min (, ) () () = l v v vv i f lir in main main in main eff osc typ () = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 2 -
max1513/max1514 tft-lcd power-supply controllers ______________________________________________________________________________________ 19 5) if v sense is greater than 100mv, the current-feed- back signal is too high and can trip the current limit before the full load current is delivered. use the cur- rent-sense configuration in figure 9 to attenuate the sense signal. define the scale factor (sf) as: calculate r s1 and r s2 : 6) if v sense is less than 80mv, the current-feedback signal is low relative to the current-limit threshold. use the figure 8 configuration, or, if good current-limit accuracy is desired, use the optional current-sense configuration in figure 10 to increase the amplitude of the sense signal. calculate r s3 and r s4 : if the 2.2? inductor used in the typical operating cir- cuit (figures 1 and 2) had a typical dcr of 24m ? and a maximum dcr of 30m ? , the rc time constant of the sense network would be: select c s = 0.1? and calculate r s : assuming ? t is 40 c and tc is 0.5%, the worst-case high sense voltage over temperature is: because v sense would be between 80mv and 100mv, the circuit in figure 8 should be used. the closest 1% standard value for r s is 909 ? . if the 2.2? inductor used in the typical operating cir- cuit (figures 1 and 2) has a typical dcr of 45m ? and a maximum dcr of 56m ? , the rc time constant of the sense network is: select c s = 0.1? and calculate r s : assuming ? t is 40 c and tc is 0.5%, the worst-case high sense voltage over temperature is: r s f s . . == 48 9 01 489 ? . . == 22 45 48 9 h m s ? vam cmv sense . . . = + () = 2 6 30 1 0 005 40 93 6 ? r s f s . . == 91 7 01 917 ? . . == 22 24 91 7 h m s ? r vv v v mv v r rrr s main in min main in min sense s sss 3 43 100 () () = + = - -- - r r sf r rsf sf s s s s 1 2 1 1 = = - sf mv v sense = 100 max1513 max1514 l r s c s v in v main c s+ c s- gate gnd fb figure 8. lossless current sensing with 80mv < v sense < 100mv max1513 max1514 l r s1 c s v in v main c s+ c s- gate gnd fb r s2 figure 9. lossless current sensing with v sense > 100mv
max1513/max1514 tft-lcd power-supply controllers 20 ______________________________________________________________________________________ because v sense would be greater than 100mv, the cir- cuit in figure 9 should be used and the scale factor is: calculate r s1 and r s2 : the closest 1% standard values for r s1 and r s2 are 866 ? and 1.13k ? , respectively. if the 2.2? inductor used in the typical operating cir- cuit (figures 1 and 2) has a typical dcr of 10m ? and a maximum dcr of 14m ? , the rc time constant of the sense network is: select c s = 0.1?, r s is: assuming ? t is 40 c and tc is 0.5%, the worst-case high sense voltage over temperature is: because v sense would be much less than 80mv, the circuit in figure 10 can be used to improve the current- limit accuracy. calculate r s3 and r s4 : the closest 1% standard values for r s3 and r s4 are 2.61k ? and 14.0 ? , respectively. output-capacitor selection the output capacitor and its equivalent series resistance (esr) affect the circuit? stability, output voltage ripple, and transient response. the output-capacitor stability requirement section discusses the output capacitance requirement based on the loop stability. this section deals with how to determine the output capacitance according to the ripple voltage and load-transient requirements. the total output voltage ripple has two components: the ohmic ripple due to the capacitor? equivalent series resistance (esr), and the capacitive ripple caused by the charging and discharging of the output capacitance: where v main is the output voltage of the step-up regu- lator, i main is the output current, c out is the output capacitance, r esr is the esr of the output capacitor, f osc is the switching frequency, and i peak is the peak inductor current (see the inductor selection section). vv v vir v i c vv vf ripple ripple esr ripple c ripple esr peak esr ripple c main out main in main osc () () () () =+ ? ? ? ? ? ? ? ? - r vv v r s s 3 4 15 4 5 1 4 0 0 044 2600 2614 2614 2600 14 . . = + = == - 5v - .5v - .1v - ?? ??? vam cmv sense = + () = 2 6 14 1 0 005 40 44 . . ? r s f s . == 220 01 2200 ? . == 22 10 220 h m s ? r r s s 1 2 489 0 571 856 856 0 571 1 0 571 1139 . . . == = = ? ? ? - sf mv mv . == 100 175 0 571 vam cmv sense = + () = 2 6 56 1 0 005 40 175 . . ? max1513 max1514 l r s3 c s v in v main c s+ c s- gate gnd fb r s4 figure 10. lossless current sensing with v sense < 80mv
max1513/max1514 tft-lcd power-supply controllers ______________________________________________________________________________________ 21 in the circuits of figures 1 and 2, the maximum total voltage ripple is 1% (peak-to-peak) of the 15v output, which corresponds to 150mv peak-to-peak ripple. a conservative way to calculate the maximum esr and minimum capacitance is to assume the esr ripple and the capacitive ripple each should not exceed 50% of the total ripple budget. where v ripple(max) is the total peak-to-peak output rip- ple. since the peak inductor current calculated in the inductor selection section is 2.6a, the maximum esr of the output capacitor should be less than 29m ? . on the other hand, only 3.1? capacitance is needed to meet the capacitive ripple requirement based on the calcula- tion. a 10? aqu-series poscap with maximum esr of 20m ? is selected for the typical operating circuits in figures 1 and 2, which meets both the voltage-ripple and minimum capacitance requirements. the typical load on the step-up regulator for source- driver applications is a large pulsed load, with a peak current of approximately 1a and a pulse width of approximately 2?. the shape of the pulse is close to triangular, so it is equivalent to a square pulse with 1a height and 1? pulse width. the total voltage dip during the pulsed load transient also has two components: the ohmic dip due to the output capacitor? esr and the capacitive dip caused by discharging the output capacitance: where i pulse is the height of the pulse load and t pulse is the pulse width. higher capacitance and lower esr result in less voltage dip. again, assume the esr dip and the capacitive dip each should not exceed 50% of the total maximum allowed output-voltage dip caused by a load pulse (v dip(max) ). for the typical load pulse described above, assuming the voltage dip must be limited to 200mv, the minimum out- put capacitor is 10?, and the maximum esr is 100m ? . the voltage rating and temperature characteristics of the output capacitor must also be considered. input-capacitor selection the input capacitor (c in ) reduces the current peaks drawn from the input supply and reduces noise injec- tion into the device. a 22? ceramic capacitor is used in the typical operating circuit (figure 1) because of the high source impedance seen in typical lab setups. actual applications usually have much lower source impedance since the step-up regulator often runs directly from the output of another regulated supply. typically, c in can be reduced below the values used in the typical operating circuit. ensure a low noise supply at in by using adequate c in . alternately, greater volt- age variation can be tolerated on c in if in is decoupled from c in using an rc lowpass filter (see r11 and c10 in figure 1). rectifier diode the max1513/max1514s?high switching frequency demands a high-speed rectifier. schottky diodes are recommended for most applications because of their fast recovery time and low forward voltage. in general, use a schottky diode with a current rating exceeding the peak inductor current calculated in the inductor selection section. output-voltage selection the output voltage of the main step-up regulator is adjustable by connecting a resistive voltage-divider from the output (v main ) to the analog ground plane with the center tap connected to fb (see figure 1). select r2 in the 10k ? to 50k ? range. calculate r1 with the following equations: where v fb , the step-up regulator? feedback set point, is 1.25v. connect the divider close to the ic. output-capacitor stability requirement the step-up regulator controller of the max1513/ max1514 uses a peak current-mode control method. the loop stability of a current-mode step-up regulator can be analyzed using a small-signal model. in contin- uous-conduction mode, the loop-gain transfer function consists of a dc loop gain, a dominant pole, a right- half-plane (rhp) zero and an esr zero. rr v v main fb 12 1 = ? ? ? ? ? ? - r v i c it v esr max dip max pulse out min pulse pulse dip max () () () () 2 2 vv v vir v it c dip dip esr dip c dip esr pulse esr dip c pulse pulse out () () () () =+ = r v i c i v vv vf esr max ripple max peak out min main ripple max main in main osc () () () () ? ? ? 2 2 -
max1513/max1514 tft-lcd power-supply controllers 22 ______________________________________________________________________________________ the dc loop gain (a dc ) is approximately: where r1 and r2 are the feedback-divider resistors (figure 1), d is the duty cycle, i main(eff) is the effec- tive maximum output current as described in the inductor selection section, 0.554 is the gain of the cur- rent-sense amplifier, and r cs is the equivalent sense- resistor value given by: where r l(typ) is the typical value of the inductor dcr, and sf is either 1 or the scale factor in step 5 of the current-sense network selection section. the frequency of the dominant pole is: the frequency of the rhp zero is: the frequency of the esr zero is: the unity-gain crossover frequency is: for stable operation, select an output capacitor with enough capacitance and a low enough esr to ensure that the dominant pole is low enough so the loop gain reaches unity well before either the esr zero or the rhp zero, the lower of which should preferably occur at or above 5 times the unity-gain frequency as long as the two zeros are well separated. calculate the mini- mum output capacitance for stable operation using: if the rhp zero and the esr zero occur simultaneously, place the dominant pole so that the unity-gain frequen- cy is less than 1/10th the frequency of the zeros. calculate the minimum output capacitance for stable operation using: where f z is the frequency of the rhp zero and the esr zero. using the typical operating circuit in figure 1 as an example: the duty cycle is 0.67, the effective maximum output current is 500ma, the inductor is 2.2? with a typical dcr of 24m ? , and the output capacitor is 10? with a maximum esr of 20m ? . the scale factor for the current-sense network is 1, so r cs is 24m ? . the dc loop gain a dc is 62, the rhp zero is at 236khz, and the esr zero is at 796khz. since the frequency of the esr zero is higher than that of the rhp zero, the unity-gain crossover frequency should be determined based on the rhp zero. the minimum output capacitance for sta- ble operation is: lead or lag compensation can be useful to compen- sate for particular component choices or to optimize the transient response for various output capacitor or inductor values. adding lead compensation (the r3/c1 network from v main to fb in figure 11) increases the loop band- width, which can increase the speed of response to transients. too much speed can destabilize the loop and is not needed or recommended for figure 1? com- ponents. lead compensation adds a zero-pole pair, providing gain at higher frequencies and increasing loop bandwidth. the frequencies of the zero and pole for lead compensation depend on the feedback-divider resistors and the rc network between v main and fb. the frequencies of the zero and pole for the lead com- pensation are: at high frequencies, r3 is effectively in parallel with r1, determining the amount of added high-frequency gain. if r3 is very large, there is no added gain and as r3 approaches zero, the added gain approaches the inverse of the feedback-divider? attenuation. a typical value for r3 is greater than 1/2 of r1. the value of c1 f rr c f r rr rr c z lead p lead _ _ = + () = + + ? ? ? ? ? ? 1 2131 1 23 12 12 1 c ma khz v f out min () . = 5 62 500 2 236 15 697 c ai fv out min dc main eff z main () () = 10 2 c ai ff v out min dc main eff z rhp z esr main () () ()() min , = [] 5 2 faf crossover dc p dominant () = f rc z esr esr out () = 1 2 fd v li z rhp main main eff () () = () 1 2 2 - f i vc p dominant main eff main out () () = 2 rsfr cs l typ () = a r rr d r v i dc cs main main eff . () = + 2 12 1 0 554 -
max1513/max1514 tft-lcd power-supply controllers ______________________________________________________________________________________ 23 determines the frequency placement of the zero and pole. a typical value of c1 is between 100pf and 10nf. when adding lead compensation, always check the loop stability by monitoring the transient response to a pulsed output load. adding lag compensation (the r4/c2 network from fb to ground in figure 11) decreases the loop bandwidth and improves fb noise immunity. lag compensation slows the transient response but can increase the stabil- ity margin, which may be needed for particular compo- nent choice or high values of fb-divider resistors. lag compensation adds a pole-zero pair, attenuating gain at higher frequencies and lowering loop bandwidth. the frequencies of the pole and zero for lag compensation depend on the feedback-divider resistors and the rc network between fb and gnd. the frequencies of the pole and zero for the lag compensation are: at high frequencies, r4 is effectively in parallel with r2, increasing the divider attenuation ratio. if r4 is very large, the attenuation ratio remains unchanged and as r4 approaches zero, the attenuation ratio approaches infinity. a typical value for r4 is greater than 0.1 times r2. if high-value divider-resistors are used, choose r4 < 1.5k ? for fb noise immunity. the value of c2 deter- mines the frequency placement of the pole and zero. a typical value of c2 is between 100pf and 1000pf. when adding lag compensation, always check the loop stability by monitoring the transient response to a pulsed output load. using lead compensation to reduce startup inrush current the digital soft-start of the main step-up regulator limits the average input current during startup. if even smoother startup is needed, add a low-frequency lead- compensation network (figure 12). the improved soft- start is active only during soft-start when the output voltage rises. positive changes in the output are instan- taneously coupled to the fb pin through d1 and the feed-forward capacitor c1. this arrangement gener- ates a smoothly rising output voltage. when the output voltage reaches regulation, capacitor c1 charges up through r3 and diode d1 turns off. if desired, c1 and r3 can be chosen to also provide some lead compen- sation in normal operation. in most applications, lead compensation in normal operation is not needed and can be avoided by making r3 large. with r3 much greater than r1, the pole and the zero in the compen- sation network are very close to one another after start- up and cancel out, eliminating the effect of the lead compensation. with r2 at 10k ? , an effective value for c1 is approximately 1000pf. charge pumps f r rr rr c f rc p lag z lag _ _ = + + ? ? ? ? ? ? = 1 24 12 12 2 1 242 max1513 max1514 r1 r2 r3 r4 c1 c2 c out r load v main fb gnd v in ld lx figure 11. feedback compensation max1513 max1514 r1 r2 r3 c1 c out v main fb gnd v in ld lx d1 figure 12. using lead compensation for improved soft-start
max1513/max1514 tft-lcd power-supply controllers 24 ______________________________________________________________________________________ selecting the number of charge-pump stages for highest efficiency, always choose the lowest num- ber of charge-pump stages that meet the output volt- age requirement. figures 13 and 14 show the positive and negative charge-pump output voltages for a given v main for one-, two-, and three-stage charge pumps. the number of positive charge-pump stages is given by: where n pos is the number of positive charge-pump stages, v gon is the gate-on linear-regulator reg p out- put, v main is the main step-up regulator output, v d is the forward-voltage drop of the charge-pump diode, and v dropout is the dropout margin for the linear reg- ulator. use v dropout = 0.3v. the number of negative charge-pump stages is given by: where n neg is the number of negative charge-pump stages, v goff is the gate-off linear-regulator reg n output, v main is the main step-up regulator output, v d is the forward-voltage drop of the charge-pump diode, and v dropout is the dropout margin for the linear reg- ulator. use v dropout = 0.3v. the above equations are derived based on the assumption that the first stage of the positive charge pump is connected to v main and the first stage of the negative charge pump is connected to ground. sometimes fractional stages are more desirable for bet- ter efficiency. this can be done by connecting the first stage to v in or another available supply. if the first charge-pump stage is powered from v in , then the above equations become: flying capacitors increasing the flying capacitor (c x ) value lowers the effective source impedance and increases the output- current capability. increasing the capacitance indefinite- ly has a negligible effect on output-current capability because the switch resistance and the diode impedance place a lower limit on the source impedance. a 0.1? ceramic capacitor works well in most low-current appli- cations. the flying capacitor? voltage rating must exceed the following: where n is the stage number in which the flying capaci- tor appears, and v main is the output voltage of the main step-up regulator. charge-pump output capacitor increasing the output capacitance or decreasing the esr reduces the output ripple voltage and the peak-to- peak voltage during load transients. with ceramic vnv cx main > n vv v vv n vv v vv pos gon dropout in main d neg goff dropout in main d = + = + - - -+ - 2 2 n vv vv neg goff dropout main d = + - - 2 n vv v vv pos gon dropout main main d = + - - 2 positive charge-pump output voltage vs. v main v main (v) g_on (v) 12 10 8 6 4 10 20 30 40 50 60 0 214 2-stage charge-pump 3-stage charge-pump v d = 0.3v to 1v 1-stage charge-pump figure 13. positive charge-pump output voltage vs. v main negative charge-pump output voltage vs. v main v main (v) g_off (v) 12 10 8 6 4 -40 -35 -30 -25 -20 -15 -10 -5 -0 -45 214 1-stage charge-pump 2-stage charge-pump 3-stage charge-pump v d = 0.3v to 1v figure 14. negative charge-pump output voltage vs. v main
max1513/max1514 tft-lcd power-supply controllers ______________________________________________________________________________________ 25 capacitors, the output voltage ripple is dominated by the capacitance value. use the following equation to approximate the required capacitor value: where c out_cp is the output capacitor of the charge pump, i load_cp is the load current of the charge pump, and v ripple_cp is the peak-to-peak value of the output ripple. the charge-pump output capacitor is typically also the input capacitor for a linear regulator. often, its value must be increased to maintain the linear regulator? stability. charge-pump rectifier diodes use low-cost silicon switching diodes with a current rating equal to or greater than twice the average charge-pump input current. if their low forward voltage helps to avoid an extra stage, some or all of the diodes can be replaced with schottky diodes with equivalent current ratings. linear-regulator controllers output-voltage selection adjust the positive linear-regulator (reg p, reg l, and reg g) output voltages by connecting a resistive volt- age-divider from their respective outputs to the analog ground plane (which connects to gnd) with the center tap connected to fb_ (figure 1). select the lower resis- tor of the divider in the range of 10k ? to 30k ? . calculate the upper resistor with the following equation: where v out _ is the output voltage of the respective lin- ear regulator, and v fb _ = 1.25v (typ). adjust the gate-off linear-regulator reg n output volt- age by connecting a resistive voltage-divider from v goff to ref with the center tap connected to fbn (figure 1). select r4 between 20k ? and 50k ? . calculate r3 with the following equation: where v fbn = 250mv, v ref = 1.25v. note that ref can only source up to 50?; using a resistor less than 20k ? for r4 results in higher bias current than ref can sup- ply without degrading ref accuracy. pass-transistor selection the pass transistor must meet specifications for current gain (h fe ), input capacitance, collector-emitter satura- tion voltage, and power dissipation. the transistor? current gain limits the guaranteed maximum output cur- rent to: where i drv is the minimum guaranteed base-drive cur- rent and r be is the pullup resistor connected between the transistor? base and emitter. furthermore, the tran- sistor? current gain increases the linear regulator? dc loop gain (see the stability requirements section), so excessive gain destabilizes the output. therefore, tran- sistors with current gain over 100 at the maximum out- put current can be difficult to stabilize and are not recommended unless needed to meet output-current requirements. the transistor? saturation voltage at the maximum out- put current determines the minimum input-to-output voltage differential that the linear regulator supports. also, the package? power dissipation limits the use- able maximum power-dissipation capability of the tran- sistor? package, and mounting must exceed the actual power dissipation in the device. the power dissipation equals the maximum load current (i load(max)_lr ) times the maximum input-to-output voltage differential: where v in(max)_lr is the maximum input voltage of the linear regulator and v out_lr is the output voltage of the linear regulator. stability requirements the max1513/max1514 linear-regulator controllers use an internal transconductance amplifier to drive an external pass transistor. the transconductance amplifi- er, the pass transistor, the base-emitter resistor, and the output capacitor determine the loop stability. the following applies equally to all linear regulators in the max1513 and max1514. the transconductance amplifier regulates the output voltage by controlling the pass transistor? base cur- rent. the total dc loop gain is approximately: pi v load max lr in max lr ()_ ()_ = () - v out_lr ii r h load max drv be fe min () () = ? ? ? ? ? ? - v be rr vv vv fbn goff ref fbn 34 = ? ? ? ? ? ? - - rr v v upper lower out fb _ _ = ? ? ? ? ? ? -1 c i fv out cp load cp osc ripple cp _ _ _ 2
max1513/max1514 tft-lcd power-supply controllers 26 ______________________________________________________________________________________ where v t is 26mv at room temperature and i bias is the current through the base-to-emitter resistor (r be ). each of the four linear-regulator controllers is designed for a different maximum output current, so they have differ- ent output drive currents and different bias currents (i bias ). each controller? bias current can be found in the electrical characteristics table. the current listed in the conditions column for the fb_ regulation voltage specification is the individual controller? bias current. the base-to-emitter resistor for each controller should be chosen to set the correct i bias : the output capacitor and the load resistance create the dominant pole in the system. however, the internal amplifier delay, the pass transistor? input capacitance, and the stray capacitance at the feedback node create additional poles in the system. the output capacitor? esr generates a zero. for proper operation, use the following equations to verify the linear regulator is prop- erly compensated: 1) first, determine the dominant pole set by the linear regulator? output capacitor and the load resistor: the unity-gain crossover of the linear regulator is: 2) the pole created by the internal amplifier delay is about 1mhz: 3) next, calculate the pole set by the transistor? input capacitance c in , the transistor? input resistance r in , and the base-to-emitter pullup resistor: g m is the transconductance of the pass transistor, and f t is the transition frequency. both parameters can be found in the transistor? data sheet. because r be is much greater than r in , the above equation can be simplified: the equation can be further simplified: 4) next, calculate the pole set by the linear regulator? feedback resistance and the capacitance between fb_ and gnd (including stray capacitance): where c fb is the capacitance between fb_ and ground, r upper is the upper resistor of the linear regulator? feedback divider, and r lower is the lower resistor of the divider. 5) next, calculate the zero caused by the output capacitor? esr: where r esr is the equivalent series resistance of c out_lr . 6) to ensure stability, choose c out_lr large enough so the crossover occurs well before the poles and zero calculated in steps 2 to 5. the poles in steps 3 and 4 generally occur at several megahertz and using ceramic capacitors ensures the esr zero occurs at several megahertz as well. placing the crossover below 500khz is sufficient to avoid the amplifier-delay pole and generally works well, unless unusual component choices or extra capac- itances move the other poles or zero below 1mhz. f cr pole esr out lr esr _ _ = 1 2 f cr r pole fb fb upper lower _ || = () 1 2 f f h pole in t fe _ = f cr pole in in in _ = 1 2 where c g f r h g in m t in fe m , , == 2 f crr pole in in be in _ || = () 1 2 f mhz pole amp _ 1 faf crossover v lr pole lr __ = f i cv pole lr load max lr out lr out lr _ ()_ __ = 2 r v i be be bias = a v ih i v vlr t bias fe load lr ref _ _ ? ? ? ? ? ? + ? ? ? ? ? ? ? ? ? ? ? ? ? ? 4 1
max1513/max1514 tft-lcd power-supply controllers ______________________________________________________________________________________ 27 pc board layout and grounding careful pc board layout is important for proper operation. use the following guidelines for good pc board layout: 1) minimize the area of high-current loops. the high- current input loop goes from the positive terminals of the input capacitors to the inductor, to the power mosfet, and to the negative terminals of the input capacitors. the high-current output loop is from the positive terminals of the input capacitors to the inductor, to the output diode, and to the positive ter- minals of the output capacitors, reconnecting between the output-capacitor and input-capacitor ground terminals. connect these loops with short, wide connections. avoid using vias in the high-cur- rent paths. if vias are unavoidable, use many vias in parallel to reduce resistance and inductance. 2) create a power ground plane consisting of the input and output-capacitor ground terminals, the source of the power mosfet, and any ground terminals of the charge-pump components. connect all of these together with short, wide traces or a small ground plane. maximizing the width of the power ground traces improves efficiency and reduces output volt- age ripple and noise spikes. create an analog ground plane consisting of the ic? backside pad, all the feedback-divider ground connections, the buffer- amplifier-divider ground connection, the ref capaci- tor ground connection, and the del capacitor ground connection. the power ground plane and the analog ground plane should be connected at only one loca- tion, which is the ic? gnd pin. all other ground con- nections, such as the in pin bypass capacitor and the linear-regulator output capacitors, should be star- connected directly to the backside pad of the ic through a via with wide traces, not otherwise connect- ing to either the power ground plane or the analog ground plane. connect the ic? backside pad to the ic? gnd pin. make no other connections between the analog and power ground planes. 3) place in and ref bypass capacitors as close to the device as possible. 4) place all feedback-voltage-divider resistors as close to their respective feedback pins as possible. the divider? center trace should be kept short. placing the resistors far away causes their fb traces to become antennas that can pick up switching noise. care should be taken to avoid running any feedback trace near the switching nodes in the step-up regu- lator and charge pumps. 5) minimize the length and maximize the width of the traces between the output capacitors and the load for best transient responses. 6) minimize the size of the switching node while keeping it wide and short. keep the switching node away from feedback nodes (fb, fbp, fbl, fbg, and fbn) and analog ground. use dc traces to shield if necessary. refer to the max1513 evaluation kit for an example of proper board layout. chip information transistor count: 4807 process: bicmos pin configuration fb cs- cs+ in 20 19 18 17 16 gate *fbg fbp drvp gnd *drvg 13 12 11 14 15 *outb *fbpb sdfr ref *supb 4 3 2 1 5 fbn del drvn drvl 6789 10 fbl max1513 max1514 top view thin qfn 4mm x 4mm *n.c. for max1514
max1513/max1514 tft-lcd power-supply controllers maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 28 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2003 maxim integrated products printed usa is a registered trademark of maxim integrated products. package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) 24l qfn thin.eps b 1 2 21-0139 package outline 12,16,20,24l qfn thin, 4x4x0.8 mm b 2 2 21-0139 package outline 12,16,20,24l qfn thin, 4x4x0.8 mm

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